View PD64001H_2985895.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l introduction _______________ the pd64001/h is a single-port power over ethernet pse (power source equipment) manager. the pse manager allows for the detection of ieee 802.3af- 2003 and ieee802.3at-draft4.2 powered devices, ensuring safe power feeding and monitoring of ethernet ports. with a minimum of external components, the pd64001/h in tegrates in a one-port or two-port poe-port switches and midspans. the pd64001/h has several operating modes, allowing it to be tailored to the customer's application, be it a switch or a midspan, ieee802.af or ieee802.3at-draft4.2-compliant, with 1-event or 2-events classification, ac or dc disconnect and strict resistor detection or legacy detection capabilities. it operates in a total stand-alone mode, with no need for user intervention. the pd64001/h supports 2-events classification and operates at iport_max currents of up to 600 ma / 720 ma (in coordination with pd64001 / PD64001H) per port, making it fully compliant with the ieee802.3at-draft4.2 this datasheet includes a complete application note and provides detailed information and circuitry design guidelines for the implementation of a 1-port power over ethernet (poe) syst em, based on microsemi?s? 1-channel poe device, the pd64001/h. this document allows the designer to integrate poe capabilities, as specified in the ieee802.3af standard into an ethernet switch, midspan or a router. applicable documents _____ ? ieee802.3af-2003 ? ieee802.3at-draft4.2 pin configuration______ features___________________ ? ieee 802.3af-2003-compliant ? ieee802.3at-draft4.2 compliant ? pd64001 supports iport_max of 600 ma ? PD64001H supports iport_max of 720 ma ? programmable solution, can be updated as the ieee802.3at standard evolves ? accurate power measuring and extremely low power dissipation ? bom and software tailored for specific application saving total solution cost ? minimal power supply stress and emi noises ? legacy (pre-standard) pd?s detection ? 1-port standalone poe control ? 1-event and 2-event classification supported ? external fet and sense resistor ? ac and dc disconnect ? detection of the disconnection method by assembled resistor ? port on/off host interface ? application uses a single operating voltage source ? direct led driving including ieee802.3at indication ? soic-20 package ? rohs compliant ? -40 o to +85 o c operating ambient temperature ordering information ______ part ilim temp. range pin package pd64001 600 ma -40 to +85 c soic-20 PD64001H 720 ma -40 to +85 c soic-20 evaluation board ordering number : pd-im-7301
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 2 main features description ___________________________________ feature description pd64001/h features ieee 802.3af-2003 compliant the pd64001/h meets all ieee-802.3af-200 3 standard require ments including: multi ? point resistor detection pd classification function ac disconnect and dc disconnect function supports back-off feature for midspan implementation ieee802.3at-draft4.2 compliant including support for high power and 2-events classification. single dc voltage input the pd64001/h requires a single dc vo ltage source: 44v to 57v. no additional voltage sources (e.g. 3.3v/5v) are requir ed for the poe system?s operation. wide temperature range: -40c to +85c the pd64001/h can operate over a wide temperature range: -40 c to +85 c. this temperature range enables the integration of the pd64001/h into small unventilated boxes and operates in harsh environments. low thermal dissipation (1 ? sense resistor) the pd64001/h has a very low thermal dissipation. the rsense in the pd64001/h applications is only 1 ? to keep the peripheral components in low temperatures as well. external power fet external mosfet is utilized to increase the flexibility of the solution, enabling it to be tailored to the customer power requirements. h/w disable port the pd64001/h utilizes a dedicated pin, allowing an immediate disconnection of the poe port. this disable-port pin input can be controlled via the host cpu. pre-standard pd detection enables the detection and powering of pre-standard powe r devices (pds). detection of cisco devices enables the detection and powering of all cisco devices including pre-standard terminals. led support direct driving of the led circuitry. this enables the designer to implement a simple led circuit, indicating whether an ieee802.3af or ieee802.3at device is connected.
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 3 maximum ratings___________ v main ??????????????? -0.3 to 60 v xresetn input voltage???????. -0.5 to 5 v application circuitry dc current ??????25 ma esd (human body model)?.??..? -2v to 2kv (1) lead temperature (soldering, 10 s)????. 300 c notes :. (1) esd testing is performed in accordance with the human body model (czap = 100 pf, rzap = 1500 ). stresses beyond those listed above may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability . operating conditions______________ ________________________ parameter min. nom. max. unit operating temperature -40 +85 c storage temperature -65 +150 c operational limitations (1) 44 50 57 v (1) to get higher power drive at the pse output ports, it is recommended to use an operating voltage source greater then 50 v. electrical characteristic s__________________ _________________ dc characteristics for digital inputs and outputs parameter symbol min. max. unit remarks pin name xreset type schmitt trigger cmos inpu t with internal pull-up high level input voltage vih 0.9 vcc vcc+0.5v v vcc = 5v low level input voltage vil -0.5v 0.2 vcc v vcc = 5v input high current iih +1 a input low current iil +1 a reset assertion time trst 2.5 s internal pull-up value rpu 30 60 k ?
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 4 dynamic characteristics parameter conditions min. typ. max. unit automatic recovery from overload shutdown tovlrec value, measured from port shutdown (can be modified through control port) 8 s automatic recovery from no- load shutdown tudlrec value, measured from port shutdown (can be modified through control port) 1 s thermal data__ _________________________ _________________ microsemi's pd64001/h enables building very low power dissipating poe devices. for a single port, the system worst case power dissipation can be calculated as follows. application disconnection method iport_max current rsense (1 ? ) diode mosfet poe manager total e ee802.3af dc 350 ma 0.12 w - 0.012 w (0.1 ? ) 0.60 w 0.73 w e ee802.3af ac 350 ma 0.12 w 0.53 w 0.012 w (0.1 ? ) 0.60 w 1.26 w e ee802.3at dc 600 ma 0.36 w - 0.036 w (0.1 ? ) 0.60 w 1 w e ee802.3at ac 600 ma 0.36 w 0.9 w 0.036 w (0.1 ? ) 0.60 w 1.9 w e ee802.3at dc 720 ma 0.52 w - 0.052 w (0.1 ? ) 0.60 w 1.17 w e ee802.3at ac 720 ma 0.52 w 1.1 w 0.052 w (0.1 ? ) 0.60 w 2.27 w
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 5 pin functionality__________ pin pin name pin type pin description 1 low_r_detect digital output low level resistance detection command 2 current_pwm digital output current limit set pwm output 3 ac_wave digital output ac disconnect output wave 4 class_pwm digital output class voltage set pwm output 5 vcc vcc 5v digital vcc 6 gnd gnd digital ground 7 led2 digital output led2 output command 8 led1 digital output led1 output command 9 high_r_detect digital output high level resistance detection command 10 xreset digital input reset on/off command from host 11 vmain_meas digital output vmain measurement command 12 port_off_imeas digital i/o port off command/ current measurement input 13 r_det_meas digital i/o port voltage measurement input 14 ac_meas digital i/o ac disconnect measurement input 15 avcc vcc 5v analog vcc 16 agnd gnd analog ground 17 pre_det digital output pre detection command 18 reserved1 digital i/o reserved for communication future use 19 rmode digital input poe manager mode setup 20 reserved2 digital i/o reserved for communication future use r mode pin_________________ this pin is connected to a resistor voltage divider. it allows the user to choose a combination of three features, as specified in the following table: r_mode voltage alt a alt b cap at/ 720 ma r8 ( )* 0.313 ? x 1.02 0.94 ? 1.25 x 2.8k 1.563 ? x x 5.23 2.19 ? 2. 5 x x 8.87 2.82 ? 3.1 x x 14.7 3.44 ? x x 25.5 4.06 ? x x x 54.9 4.68 ? 5 v x x x no * r8 pull-down's value depends on the actual mode, while for all of the modes, r7 pull-up's value is 10kohm. the alt a / alt b option selects between a pse alternative a or pse alternative b as specified in section 33.2 of the standard. to implement a midspan pse, use the alt b option. the at option is ieee802.3at- compliant in accordance with the ieee802.3at-draft4.2. the cap option is pre- standard capacitor detection mode. general application description the circuit comprises the following major interfaces with the host board: control a reset control signal driven by the switch circuitry is used to reset the poe circuit. this signal should be optically coupled by the host in order to maintain the requirements for the 1500 vrms isolation. power supply mains the poe system operates over a range of 44v to 57v. this power must be isolated from the switch supply and chassis by 1500 vrms. grounds there are several grounds used in the system: chassis, digital and analog. the chassis ground is connected to the switch?s chassis ground.
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 6 this ground plane should be 1500vrms isolated from the poe circuitry as well as the power supply for the poe circuitry. the digital and analog grounds are electrically the same grou nd. however, in order to reduce noise coupling, t he grounds are physically separated and connected only at a single point. 5v regulator a single port application includes a 5v regulator (vcc) fed by the vmain through d1 and d3 zener diodes and provides up to 25 ma used to power the cpu and peripheral components in the poe domain. using a 3% accuracy power supply for the poe circuitry d1 and d3 should be selected according to the power supply nominal voltage set point using the following graph. d1 voltage plus d3 voltage as seen in the below graph, should be evenly divided between the two zener diodes. d1+d3 voltage (vdc) if an adequate 5v power source is available, the 5v regulation circuitry can be removed and the zener diodes may be replaced with lower current (5 ma) zener diodes but with same voltage requirements. detailed application description____________ (see figure 2 ) the pd64001/h performs a multitude of internal operations and poe functions, requiring a bare minimum of external components. the device is based on atmel's attiny461 mcu. each pd64001/h device handles one port. figure 2 shows the device with its related components for a 1-port configuration. mode configuration - set by the resistor divider (r7/r8) tied in to the rmode line. the values are fixed for each mode of operation and described in the "r mode pin" section in this document. line detection circuitry ? when performing a line detection procedure, the poe device utilizes certain voltage levels over the output port. these levels are produced by switched resistor dividers and sensed by the pd64001/h in order to confirm a valid pd connection. current loop circuitry ? the current is controlled by q4 mosfet. the pd64001/h provides pwm signal via pin#2 with a constant duty cycle (depending on the r mode configuration). this pwm signal is filtered and utilized as the current limit circuitry voltage reference. sense resistors ? for each powered port, two 2-ohm 2010 (1%) resistors connected in parallel (1-ohm equivalent) are used in series with the output (r9, r11). in ca ses where the ambient temperature drops below 70 0 c, or the product does not have to meet 802.3at power, a single 1-ohm 2010 (1%) resistor is adequate. classification circuitry ? upon port investigation completion, the pd should be classified by its classification current signature. two voltage levels are set over the port, derived from a reference voltage filtered from pd64001/h's pin#4 (pwm signal) and sent to an operational amplifier controlling q4. output port - the load resistance of the pd attached to the port is presented in parallel with r13. the resulting voltage developed across both resistances is monitored to establish the 802.3af/at compatibility. led indication - the 1 port application may use the pd64001/h led1 and led2 pins for system status indications as shown below: r30 20k pd-1206 r31 1k vmain r33 1k led2 led1 d10 vcc vmain_ok
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 7 pd operating status led1 led2 ieee802.3af ? on on off ieee802.3at ? on on on ieee802.3af - ovl/sc blink at 1hz off ieee802.3at - ovl/sc blink at 1hz blink at 1hz vmain out of range blink at 4hz off layout design guidelines (see figure 3 for layout example) isolation & termination ? as specified in the ieee standard, certain isolation requirements need to be met in all poe equipment. in addition, emi limitations should be considered, according to fcc and european en regulations. these requirements are taken into account by poe switch vendors, while designing the switch circuitry. however, when a poe device is integrated into a switch, special design considerations must be taken into account, due to the unique combination of data and power circuitries. the next paragraphs define these requirements and provide recommendations for their implementation, so as to assist designers in meeting those requirements and in integrating poe chipset. isolation - as specified in the ieee standard, 1500vac rms isolation is required between the main board circuitry of the switch, including protective and frame ground and the poe circuitry. isolating the stacked modular jack assembly the ieee standard requires 1500 vrms isolation between poe voltages and frame ground (egnd). note that rj-45 jack assemblies may have a metal cover that reach almost to the pcb surface. proper traces clearance (at least 80 mils) are to be maintained between egnd traces for the rj-45 modular jack assembly metal covering and adjacent circuit paths and components. to prevent 1500 vrms isolation violation, it is necessary to provide lay out clearances of poe traces, on the top layer, in the vicinity of the rj-45 connector assemblies. poe output ports? filtering and terminations: a switch normally creates a noisy environment. in order to meet the emi requirements, good filtering and line terminations may be needed when connecting the poe circuit outputs to the switch circuitry (see figure 1). note that in most poe systems, it is recommended to use 0 ohms resistors for r100 and r101. however, certain systems may benefit from the 75ohm value. it is recommended that filtering prov isions are utilized. a circuitry for the recommended filter includes: ? a common mode choke for conducted emi performances ? output differential capacitor filter for radiated emi performances ? y-capacitive/resistive network to chassis since each system is a unique emi case, this circuit is a good starting point for emi suppression. out (+) out (-) port_ pos port_neg r100 r101 c100 c101 l100 c102 c103 figure 1: recommended emi filter note for best emi performance and to avoid additional noise accumulated on the lines between the filter and the port connectors, it is recommended to assemble this circuitry as close as possible to the port connectors. poe circuitry trace clearance - poe technology involves voltages as high as 57vdc. thus, plan adjacent traces for 100v operational creepage. operational creepage should be maintained to prevent breakdown between traces carrying these potentials. locating poe circuitry in a switch - placement of the poe circuitry must be as close as possible to the
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 8 switch?s pulse transformers, to minimize the length of high current traces as well as rfi pick-up. ground & power planes - as the chipset poe solution is a mixed-signal (analog and digital) circuitry, special care must be taken when routing the ground and power signals lines. ground planes are crucial for proper operation and should be designed in accordance with the following guidelines: ? separate analog and digital grounds, with a gap of at least 40 mils. ? earth ground is used to tie in the metal frame of the rj-45 connectors. this ground is to be routed separately and connected to the switch?s metal chassis/enclosure ? only a single connection point is to be used between the digital and analog grounds, in order to prevent ground loop currents. this connection is to be accomplished near the current loop senses resistors r9, r11 ? the traces from vmain input to the port output, poe switch (q4) and sense resistors must be designed to carry 1a continuous current peripheral components ? ? to prevent hot spots on the peripheral components minimum distance of 5mm should be maintained between the powering zener diodes d1 and d3, the linear regulator u1, sense resistors r9 and r11 (placed together) and current limit mosfet q4. other methods may be used in order to dissipate the heat, such as thermal copper planes at the top and bottom layers with heat transfer vias between them ? filtering capacitors for vcc (u4 pins 5, 15) are to be located close to these pins ? the input and output capacitors of the linear regulator should be placed close to the regulator pins ? the trace connecting the power mosfet and the sense resistors should be as short as possible and the current loop sampling trace should be connected as close as possible to the sense resistors specifying poe power supply _____ an intelligent selection of the power supply to be used in conjunction with the 1-port system may avoid the use of additional filtering circuitry (e.g. front end common mode filter) for standard regulatory approval. electromagnetic compatibility requirements ? typical power over ethernet (poe) technology systems are classified in most applications as information technology equipment (i.t.e). the i.t.e should comply with three tests in order to get a standard approval: ? conducted disturbance at mains ports (ac input) ? radiated disturbance at a measuring distance of 10m ? conducted common mode disturbance at telecommunication ports (output port containing ethernet+power) a relatively new requirement of en55022 that is mandatory as of august 1st, 2007 in most cases, the pse side of a poe system incorporates a main ac to dc switching mode power supply (smps) required for delivery of a dc power to the poe ports. this power supply is most likely to be the largest source for common mode noise injection on the output ports wires, as its noisy output voltage is super-imposed on the telecommunication wires by the poe control circuitry. the common mode noise is generated by the high dv/dt and di/dt switching rates in power mosfets and high speed rectifying diodes, common in smps designs. as the system designer is usually responsible for specifying this power supply, it is important to add the standard requirements to the power supply specifications and specify a specific reference test setup to be used for the tests. this reference test setup should be as similar as possible to the final product, which means using the same box material (plastic or metal) and the same distance and polarity between the smps and poe circuitry.
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 9 when specifying and testing the power supply, it is important to assure that test requirements are met under all load conditions and line voltages. most switching power supp lies designs will exhibit the highest conducted noise at the maximum load and the lowest line voltage. however, other cases may also exist. as it is impractical to go through all loads span, it is recommended to test at full load, medium load and minimum load. the cables suggested for use are cat 5 utp cables of at least 5m. (both utp and ftp cables shall be tested for compliance in the final system tests). note that the standard deals with shielded and un- shielded cables independently and the appropriate test procedure shall be performed. resistive loads are selected to remove possible noise injection from the pd side, leaving only the main power supply as the source of noise. for radiated disturbance using a proper smps layout (short power patch and avoiding current loops) may contribute to disturbance reduction. for additional reduction if needed, full or partial metal frame connected to mains earth may be used. immunity requirements ? an i.t.e should comply with en55024 in order to get a standard approval: most power supply manufacturers are familiar with the standard requirements from the power supply and know how to design the power supply to comply with it. the requirements from the power supply's ac input power port are: ? immunity to radio frequency continuous conducted according to iec61000-4-6 ? voltage dips and voltage interruptions according to iec61000-4-11 ? surges according to iec61000-4-5 ? fast transients according to iec61000-4-4 ? the poe circuitry may also be exposed to immunity tests on the telecommunication ports such as: ? radio frequency continuous conducted according to iec61000-4-6 ? surge line to earth according to iec61000- 4-5 (usually for port that may connect to outdoor cables) ? fast transients according to iec61000-4-4 and the poe enclosure port exposed to: ? radio frequency electromagnetic field immunity according to iec61000-4-3 ? esd electrostatic-discharge according to iec61000-4-2 to satisfy these tests requirements on the telecommunication lines, "y" capacitors to the chassis (earth) will create a current path to earth. it is a good practice to have two "y" capacitors of 10nf/2000v each at the power supply output positive and negative nodes to earth, to create a current path for surge generated on the telecommunication lines (respect to earth). the system may benefit from two small "y" 1nf/2000v capacitors, on the poe positive and negative output lines close to the output rj45 connector, by increasing system immunity to esd.
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 10 note 2 - this short is performed manually upon completion of the pcb layout in order to connect both grounds at a single point c12 100n 100v x7 r pd-1206 1 2 vport_neg q4 pd-dpak fqd19n10 3 1 2 d3 do-41 1n4745ap 2 1 r24 4.87k pd-0805 c4 50v 100n x7r pd-0805 1 2 v_ldo vmain_meas u1 pd-so8 mc78l05abdr2g vin 8 vout 1 gnd 2 gnd#3 3 gnd#6 6 gnd#7 7 nc1 4 nc2 5 r23 402k pd-0805 c15 10v 2.2u x7r pd-0805 1 2 notes xreset q6 pd-sot23 bss123 2 1 3 r25 140k pd-0805 port_off_imeas v_ldo r7 10k pd-0603 v_ldo q1 pd-sot23 bss123 2 1 3 u3 short c3 100n 16v x7 r pd-0603 1 2 q5 pd-sot23 bss123 2 1 3 note 3 q2 pd-sot23 bss123 2 1 3 note 3 ? optional connector for software upgrading low_r_detect c14 470p 50v x7r pd-0603 1 2 vcc r18 51.1k pd-0603 vcc low_r_detect current_pwm class_pwm xreset ac_wave high_r_detect port_off_imeas r17 402k pd-0805 vcc pre_detect vmain_meas rmode current_pwm c1 1n 50v x7 r pd-0603 1 2 vcc r2 10k pd-0603 d5 pd-sma gs1g 2 1 + - u2a pd-so8 ka358adtf_nl 3 2 1 8 4 + - u2b pd-so8 ka358adtf_nl 5 6 7 8 4 class_pwm c21 50v 1uf x7 r pd-1206 1 2 pre_detect r13 75k pd-0805 c10 1n 50v x7r pd-0603 1 2 r15 5.11k pd-0603 r_det_meas_class_off vmain note 1 note 1 - the zener diodes d1and d3 should be determine according the poe power supply set voltage r4 10k pd-0603 1 2 r26 140k pd-0805 low_r_detect r12 1k pd-0603 j2 neltron-2213s-6p ch81-062v200 n.c 1 2 3 4 5 6 c19 100n 16v x7 r pd-0603 1 2 d2 pd-sot23 bat64 1 3 2 c18 25v 22n x7 r pd-0603 1 2 c8 100n 16v x7 r pd-0603 1 2 vmain vcc vcc r8 r mode pd-0603 u4 pd-sow20 attiny 461-20su pb0 1 pb1 2 pb2 3 pb3 4 vcc 5 gnd 6 pb4 7 pb5 8 pb6 9 pb7 10 pa7 11 pa6 12 pa5 13 pa4 14 avcc 15 agnd 16 pa3 17 pa2 18 pa1 19 pa0 20 regulator ac_wave r5 215k pd-0805 r9 2 pd-2010 r_det_meas_class_off r6 215k pd-0805 r1 15.4k pd-0603 r11 2 pd-2010 r_det_meas_class_off vcc r16 1.24k pd-0603 note 2 d1 do-41 1n4745ap 2 1 vport_pos current_pwm high_r_detect c5 16v 3.3nf x7 r pd-0603 1 2 figure 2: one port chipset schematic diagram
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 11 figure 3: layout example of component and print side
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 12 bill of materials for a po e system______ ____________________ block qty reference description pcb footp rint manufac turer manufacturer's part number 2 c1,c10 cap crm 1nf 50v 10% x7r 0603 smt pd-0603 epcos b37931-k5102-k60 3 c3,c8,c19 cap crm 100nf 16v 10% x7r 0603 smt pd-0603 epcos b37931k9104k60 1 c4 cap crm 100nf 50v 10% x7r 0805 smt pd-0805 samsung cl21b104kbac 1 c5 cap crm 3.3nf 16v 10% x7r 0603 smt pd-0603 tdk c1608x7r1c332k 1 c12 cap crm 100nf 100v 10% x7r 1206 smt pd-1206 samsung cl31b104kcfnnn e 1 c14 cap crm 470pf 50v 10% x7r 0603 smt pd-0603 epcos b37931-k5471-k60 1 c15 cap crm 2.2uf 10v 10% x7r 0805 smt pd-0805 samsung cl21b225kpfnnn c 1 c18 cap crm 22nf 25v 10% x7r 0603 smt pd-0603 rohm mch185cn223kk 1 c21 cap crm 1uf 50v 10% x7r 1206 smt pd-1206 tdk c3216x7r1h105k 2 d1,d3 (1) diode 16v 1w 5% d041 insert do-41 microsemi 1n4745ap 1 d2 diode schot 30v 200 ma sot23 smt pd-sot23 infineon bat64 1 d5 diode rec 400v 1a sma smt pd-sma pan jit gs1g 4 q1,q2,q5,q 6 fet nch 100v 0.15a 6r logic level sot23 pd-sot23 infineon bss123 1 q4 fet nch 100v 13a 0.12r dpak smt pd-dpak fairchild fqd19n10 1 r1 res 15.4k 62.5 mw 1% 0603 smt pd-0603 samsung rc1608f1542cs 3 r2,r4,r7 res 10k 62.5 mw 1%0603 smt pd-0603 rohm mcr03ezhefx100 2 2 r5,r6 res 215k 0.125 w 0.5% 0805 smt pd-0805 yageo rt0805drd07215k 1 r8 r mode pd-0603 2 r9,r11 res 2r 0.75 w 1% 2010 smt pd-2010 koa rk73h2htte2r00f 1 r12 res 1k 62.5 mw 1%0603 smt pd-0603 samsung rc1608f1001cs 1 r13 res 75k 125 mw 1%0805 smt pd-0805 rohm mcr10ezhef7502 1 r15 res 5.11k 62.5 mw 1%0603 smt pd-0603 samsung rc1608f5111cs 1 r16 res 1.24k 62.5 mw 1%0603 smt pd-0603 asj cr16-1241fl 2 r17,r23 res 402k 125 mw 1%0805 smt pd-0805 yageo rc0805frf07402k 1 r18 res 51.1k 62.5 mw 1%0603 smt pd-0603 samsung rc1608f5112cs 1 r24 res 4.87k 125 mw 1%0805 smt pd-0805 samsung rc2012f4871cs 2 r25,r26 res 140k 1%125 mw 0805 smt pd-0805 samsung rc2012f1403cs 1 u1 ic volt reg 5v 0.1a 4% so8 smt pd-so8 on semi mc78l05abdr2g 1 u2 (2) ic op amp dual so8 smt pd-so8 fairchild ka358adtf_nl 1 port chips et circui try 1 u4 1-port ieee802.3at poe pse manager pd- sow20 microsemi pd64001/h 1. select these diodes as specified in "5v regulator" section on page 4. 2. this operational amplifier should be use for appl ications intend for ambient temperature range of 0 c to +70 c. for ambient temperature range of -25 c to +85 c replace it with ka258adtf_nl. for ambient temperature range of -40 c to +85 c replace it with ti's tlv342aid.
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 13 package information ____________________ ____________________ microsemi?s pd64001/h is housed in a 20-lead, 0.300" wide, plastic gull wing small outline package (soic).
p p d d 6 6 4 4 0 0 0 0 1 1 / / h h 1 1 - - p p o o r r t t p p o o e e m m a a n n a a g g e e r r d d a a t t a a s s h h e e e e t t c c o o m m p p a a n n y y c c o o n n f f i i d d e e n n t t i i a a l l copyright ? 2009 microsemi rev. 1.3 2009-02-23 analog mixed signal group 2381 morse avenue, irvine, ca 92614, usa; phone (usa): (800) 713-4113, (row): (949) 221-7100 fax: (949) 756-0308 14 the information contained in the document is propri etary and confidential in formation of microsemi and cannot be copied, published, uploaded, posted, transm itted, distributed or disclosed or used without the express duly signed written consent of microsemi if the re cipient of this document has entered into a disclosure agreement with microsemi, then the terms of such agreem ent will also apply . this document and the information contained herein may not be modified, by any person ot her than authorized personnel of microsemi. no license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the informati on, either expressly, by implication, inducement, estoppels or otherwise. any license under such intellectual property rights must be ex press and approved by microsemi in writing signed by an officer of microsemi. microsemi reserves the right to change the configuration, functi onality and performance of its products at anytime without any notice. this product has been subject to limit ed testing and should not be used in conjunction with life- support or other mission-critical equipment or applic ations. microsemi assumes no liability whatsoever, and microsemi disclaims any express or im plied warranty, relating to sale and/or use of microsemi products including liability or warranties relating to fit ness for a particular purpose, merchantab ility, or infringement of any patent, copyright or other intellectual property right. the pro duct is subject to other terms and conditions which can be located on the web at http://www.microsemi.com/legal/tnc.asp revision history revision level / date para. affected description 1.0 / 26 july. 08 - initial release 1.1 / 23 feb. 09 - temperature range update. 1.2 / may 23. 09 - added PD64001H p/n 1.3 / aug 11. 09 formatting, englsih ? 2009 microsemi corp. all rights reserved. for support contact: customer.care_amsg@microsemi.com visit our web site at: http://www.microsemi.com/powerdsine/support/ catalog number: 06-0068-058

▲Up To Search▲

Price & Availability of PD64001H

	To Download PD64001H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .